1. Field of the Invention
The present invention generally relates to floating point units and, more particularly, to a floating point unit having preload registers for holding next operands to be used during execution of future instructions.
2. Description of Related Art
Floating point units (or "FPUS") which performing arithmetic operations such as add and multiply have long been known in the art. FPUs typically include a register array which holds both input operands and results. While operands are often imported into the FPU, the architecture for certain FPUs is structured such that arithmetic operations must include the input operand located at the top of the register array (or "TOA") as one of the operands. Upon completion of the arithmetic operation, the result is then written to the TOA.
While FPUs are not ordinarily provided with instruction queues capable of holding multiple floating point instructions, certain FPUs are provided with 2-deep instruction queues or, in some cases, 4-deep instruction queues, respectively capable of holding up to two or four floating point instructions issued to it by the CPU core via the load/store pipe stage. Since a next instruction can be issued to the FPU before the prior instruction has been completed, the 2-deep or 4-deep instruction queue has improved the pipelining of instructions to the FPU. However, regardless of whether an FPU is provided with an instruction queue, if an FPU's architecture is structured such that the execution of the next instruction requires the result written to the TOA at the completion of the prior instruction, queueing of instructions in an instruction queue does not always result in an improvement in performance by the FPU in executing its instructions.
One example of a microprocessor characterized by a register array architecture in which the result of arithmetic operations are written to the TOA is the X87 microprocessor. By exploiting this characteristic of the X87 architecture, decoded instructions being held by the 4-deep instruction queue may be used to enhance the performance of the X87 microprocessor if such a microprocessor was provided with preload registers for holding next operands such that a next instruction may be initiated before a prior instruction has finished.
Thus, it can be readily seen from the foregoing that it would be desirable to improve the performance of an FPU by providing it with preload registers which enable initiation of a next instruction held in a instruction queue. It is, therefore, the object of this invention to provide such an FPU.